sm120

Optimized SGLang runtime for Qwen3.8-27B FP8 with DFlash2 and Qwen3.8 Flash-Next NVFP4 with FR-Spec on one NVIDIA RTX PRO 6000 Blackwell 96 GB GPU (SM120): 524K context, HiCache and NIXL.

GLM-5.2-NVFP4-REAP-469B serving on SM120 (4× RTX PRO 6000 Blackwell) — one-command vLLM launch recipe, 250K context, DeepSeek Sparse Attention + MTP speculative decode

NVFP4 inference on Blackwell GeForce (RTX 5090/5080/5070 Ti/RTX PRO 6000) — SM120 patches for vLLM + FlashInfer + CUTLASS. 175 tok/s on Qwen3.6-35B MoE.

Reproducible SGLang recipe + public prebuilt image (ghcr.io) for DeepSeek-V4-Flash-0731 on 4x RTX PRO 6000 Blackwell (SM120): TP4/DP4/EP4, 1M ctx, benchmarks, and the DSPARK draft-depth corruption boundary

Reproducible recipe: serve abliterated Gemma-4-12B (gemma4_unified) at 50-118 tok/s on no-NVLink Blackwell (SM120) via vLLM nightly + ModelOpt FP8/NVFP4 + MTP spec-decode.

World's first hazard checker for NVIDIA Blackwell (sm_120), with an assembler and scheduler matched against their own compiler byte for byte. The check they never shipped.

Lna-Lab production pipeline: GGUF -> modelopt-format NVFP4 + working MTP head for vLLM on RTX PRO 6000 Blackwell (SM120). Stages 2 (NVFP4) and 3 (MTP graft) are Lna-Lab originals; stage 1 (GGUF->bf16) reuses li-yifei/gguf-to-nvfp4.

Rust-native MoE inference runtime with custom CUDA kernels for Blackwell GPUs. Includes DFlash speculative decoding, multi-tier Engram memory, and entropy-adaptive routing. Targets Qwen3.5-35B-A3B on a single RTX 5060 Ti 16GB.

SGLang Qwen3.8-Flash-Next FP8 for dual SM120 RTX PRO 6000 Blackwell

Optimized vLLM deployment for NVIDIA Blackwell (RTX 5090) on Linux Kernel 6.14. Resolves SM_120 kernel incompatibilities, P2P deadlocks, and memory fragmentation for high-performance LLM inference.

High-performance runtime extensions for vLLM.

AEON vLLM Ultimate RTX — vLLM 0.27.1 from source for RTX 5090 / Blackwell sm_120 / NVFP4. NOT for DGX Spark / GB10 / sm_121a.

VPN-free Prebuilt PyTorch 2.9.0 for CUDA 12.8 + sm_120 (RTX 5080)

vLLM + FlashInfer source integration for GLM-5.3-Flash on SM120 / RTX PRO 6000 Blackwell

Hand-written LLM inference CUDA kernels for consumer Blackwell (RTX 5060 Ti / sm_120) — 1.05x vLLM's Marlin at batch-1 decode, with reproducible Nsight Compute evidence for every level.

The only deployed sparse FP4 GEMM on SM120: beats CUTLASS 80b on every shape, wins end-to-end request latency in 81 of 112 serving regimes vs dense NVFP4.

Ornith-1.5-35B NVFP4-W4A16 + BF16 MTP via SGLang on SM12X (SM120/SM121). Click-run serve + SM12X-LLM-BENCH claim row.

Drop-in exact bf16 flash-attention for CUDA with a deterministic backward, tuned for Blackwell (sm_120 / RTX 5090).

Single-node 8x RTX 6000D deployment of DeepSeek-V4.1-Flash (TP=8): SM120 patches, DSpark speculative decoding, FP8 KV, and measured PCIe topology / NCCL P2P analysis. 力数智能科技（江苏）有限公司 / lexdata

NATTEN 0.21.6 Windows wheel for Python 3.13, PyTorch 2.10, CUDA 13.0, NVIDIA Blackwell sm_120 / RTX 5090; Pixal3D-ComfyUI compatible.